Semiconductor switch array with electrostatic discharge protection and method of fabricating

ABSTRACT

A method of inhibiting electrostatic discharge damage to an array of semiconductor switches (21) formed on a common substrate and arranged in rows and columns comprises the steps of: during formation of gate lines (24) that interconnect one of the rows and columns of the array, connecting one end of each gate line directly to a shorting ring (52) and another end of each gate line to a shorting ring (56) via a protection element (54); during formation of the source lines (26) that interconnect the other of the rows or columns of the array, connecting one end of each source line directly to a shorting ring (56) and connecting another end of each source line to a shorting ring (56) via a protection element (58); and electrically coupling the shorting rings (52, 56). A semiconductor switch array (21) incorporating electrostatic discharge protection (50) is also provided.

TECHNICAL FIELD

The present invention relates to a method of protecting a semiconductorswitch array from electrostatic discharge damage and to a semiconductorswitch array incorporating electrostatic discharge protection.

BACKGROUND ART

Electrostatic discharge (ESD) damage is a well known phenomenon and canoccur during the fabrication of semiconductor devices such asmetal-oxide semiconductor (MOS) structures. In structures of thisnature, ESD damage can result in gate insulating layer breakdown, largeshifts in threshold voltage and large leakage currents between the gateand source electrodes or gate and drain electrodes.

ESD damage is a more pronounced problem during the fabrication of thinfilm transistor (TFT) switch arrays for use in liquid crystal displaysor in flat panel detectors for radiation imaging. This is due to thefact that the TFT switches are formed on an insulating substrate(typically glass) and thus, the source and drain electrodes may chargeto a very high voltage. Also, because peripheral circuits to which theTFT switch array is to be connected are generally not formed on the samesubstrate as the TFT switch array, the gate and source lines must extendfrom the TFT switch array sufficiently to allow the peripheral circuitsto be connected to the TFT switch array via wire bonding pads. Anystatic charge picked up by the gate and source lines is transferred tothe gate and source electrodes of the TFT switches as well as to theintersecting nodes of the gate and source lines where the static chargeis held. If the static charge reaches a high enough level, thedielectric gate insulating layer between the gate and source electrodesmay breakdown. Even if this breakdown can be avoided, the voltagedifferential between the gate and source electrodes or gate and drainelectrodes caused by this held static charge may cause the thresholdvoltage of the TFT switches to shift in either a positive or negativedirection.

Recently, a large amount of attention has been given to the problemsresulting from ESD damage especially in active matrix liquid crystaldisplays and flat panel detectors for radiation imaging. It is nowbelieved that ESD damage is also caused by equipment related problemsduring the fabrication, handling and testing of these types of devices.The trends to use higher throughput equipment with higher speedsubstrate handling as well as to downscale during the fabricationprocess to reduce metal line width and reduce parasitic capacitance inthe TFT switches decrease ESD immunity.

One common ESD damage protection circuit used with TFT switch arraysmakes use of closed shorting bars surrounding the TFT switch array tolink all of the source lines and the gate lines of the TFT switch arraytogether. The shorting bar associated with the gate lines is formed atthe time the gate lines are formed while the shorting bar associatedwith the source lines is formed at the time the source lines are formed.The two shorting bars are electrically connected through vias formed inthe TFT switch array structure. Because the shorting bars connect thegate and source electrodes of all of the TFT switches in the array, thegate and source electrodes remain at the same potential throughout thefabrication process. This prevents any voltage differentials fromoccurring across the gate and source electrodes and therefore, inhibitsESD damage at these electrodes.

Once the TFT switch array has been completely fabricated, the shortingbars are removed by cutting off part of the glass substrate where theshorting bars located. This cutting process is done before theindividual TFT switches are tested and before the gate and source linesare connected to peripheral circuits.

Although the above ESD damage protection circuit is widely used, oncethe shorting bars have been removed, to ESD damage protection remains.This poses problems since ESD damage often occurs during testing of theTFT switches and during bonding of the gate and source lines toperipheral equipment. This is in view of the fact that at this stage,the TFT switch array is handled by individuals and contacted withelectronic measuring equipment.

Another ESD damage protection network for TFT switch arrays is disclosedin U.S. Pat. No. 4,803,536. This ESD damage protection network makes useof a strip of N⁺ amorphous silicon resistive material film extending toall of the bonding pads. The value of the resistive material film is atleast an order of magnitude greater than the impedance of externaldriver circuits connected to the bonding pads. By manipulating theresistance of the resistive material film, static charges disperse toall of the gate and source lines with an RC constant. Althoughindividual TFT switches can be tested without removing the resistivematerial film, the resistive material film crosses over all of the gateand source lines. This causes crosstalk and electronic noise which incertain applications, such as x-ray imaging where signal currents aresmall, are serious problems.

U.S. Pat. No. 5,313,319 discloses yet another ESD protection circuit fora TFT switch array. This protection circuit includes static protectioncapacitors formed on the substrate of the TFT switch array between thegate and source lines. The thickness of the static protection capacitorsare chosen to ensure that they breakdown due to static charges beforeESD damage to the TFT switches occurs. Unfortunately, the staticprotection capacitors increase stray capacitance in the TFT switch arraythereby increasing electronic noise making the TFT switch arrayunsuitable for many applications.

Japanese Patent Nos. JPA2-61618, JPA62-198826 and JPA1-303416 and U.S.Pat. No. 5,371,351 disclose an ESD protection circuit for a TFT switcharray which makes use of photodiodes formed of an a-Si film. Thephotodiodes connect the gate lines with the source lines to minimize anypotential voltage difference between them. When the photodiodes areilluminated, the resistance of the protection circuit decreasesdramatically creating short circuits between the gate and source lines.When testing individual TFT switches, or when operating the TFT switcharray in normal conditions, no incident light is permitted to impinge onthe photodiodes. This keeps the resistance of the protection circuitvery high to minimize crosstalk and leakage currents.

U.S. Pat. No. 5,220,443 discloses an ESD protection circuit for a TFTswitch array. The protection circuit includes a common electrodeinterconnecting the gate and source lines. Non-linear resistive elementshaving a resistance that decreases with an increase in voltage areconnected between the gate and source lines. The non-linear resistiveelements are realized using two back to back thin film diodes. Becausethe resistive elements provide a large resistance between the gate andsource lines, individual TFT switches can be tested without cutting theglass substrate. Even after cutting the glass substrate, some of thenon-linear resistive elements remain to improve the immunity of the TFTswitch array to ESD damage. However, the immunity of the TFT switcharray to ESD damage after cutting is significantly less than beforecutting.

The prior art ESD protection circuits referred to above all have somecommon drawbacks. Firstly, none of the ESD protection circuits protectthe TFT switch array from the first manufacturing stage (usually gateline formation) to the last manufacturing stage (usually wire bonding).During the manufacture of TFT switch arrays for liquid crystal displays,it has been found that ESD damage may occur during the process of spincoating or stripping photoresist, during the cleaning process using DIwater, and during plasma etching. These processes are often performedprior to the completion of the TFT switch array structure. Isolating thegate lines before finishing source line metallization as suggested inthe prior art may result in the build up of electrostatic charge on thegate lines. Electrostatic charges on the gate lines may become buriedunder the dielectric film forming the gate insulating layer and incubateuntil later stages in the manufacturing process. During these laterstages, the buried electrostatic charges may move along the gate linesand concentrate at a few points or boundary lines causing a breakdown inthe dielectric gate insulating layer.

In addition, in some instances since the gate and source lines areinterconnected by protection elements, a failure in the connectionbetween a gate or source line and a protection element will result inthe gate or source line being isolated from the common electrode.

In the case of U.S. Pat. No. 5,220,443, although some ESD damageprotection circuitry remains on the substrate during the wire bondingprocess, the impedance between an arbitrary gate line and a source linemay become too large to discharge electrostatic charge quickly enough toavoid ESD damage. Accordingly, better protection against ESD damage isdesired.

It is therefore an object of the present invention to provide a reliablemethod of protecting a semiconductor switch array from ESD damage and asemiconductor switch array incorporating electrostatic dischargeprotection which obviates or mitigates at least one of theabove-described disadvantages.

SUMMARY OF THE INVENTION

According to one aspect of the present invention there is provided amethod of inhibiting electrostatic discharge damage to an array ofsemiconductor switches formed on a common substrate and arranged in rowsand columns, individual ones of one of the rows or columns of said arraybeing interconnected by source lines and the individual ones of theother of the rows or columns of said array being interconnected by gatelines, said method comprising the steps of:

during formation of said gate lines, connecting one end of each gateline directly to a shorting element and another end of each gate line toa shorting element via a protection element;

during formation of said source lines, connecting one end of each sourceline directly to a shorting element and connecting another end of eachsource line to a shorting element via a protection element; and

electrically coupling said shorting elements.

According to yet another aspect of the present invention there isprovided a semiconductor switch array incorporating electrostaticdischarge protection comprising:

an array of semiconductor switches formed on a common substrate andarranged in rows and columns, the individual ones of one of the rows orcolumns of said array being interconnected by source lines and theindividual ones of the other of said rows or columns beinginterconnected by gate lines; and

a pair of electrically coupled shorting elements formed on saidsubstrate, each of said gate and source lines being connected to one ofsaid shorting elements directly and to one of said shorting elements viaa protection element.

In one embodiment, it is preferred that the method further comprises thestep of connecting the one and another ends of each of the source linesto a first shorting element, connecting the one ends of each of the gatelines to a second shorting element and the another ends of each of thegate lines to the first shorting element electrically coupling the firstand second shorting elements.

In another embodiment, it is preferred that the method further comprisesthe step of connecting the one ends of the source and gate lines to afirst shorting element, connecting the another ends of the source andgate lines to a second shorting element and electrically coupling thefirst and second shorting elements. In this case, it is also preferredthat the one and another ends of the source and gate lines alternatebetween opposite sides of the array. In both embodiments, it ispreferred that the protection elements are in the form of resistiveprotection elements.

The present invention provides advantages in that the ESD damageprotection is maintained throughout the entire manufacturing and testingprocess of the semiconductor switch array and is fully compatible withconventional semiconductor switch array fabrication processes.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described more fullywith reference to the accompanying drawings in which:

FIG. 1 is a schematic of a flat panel detector for radiation imagingincorporating a TFT switch array;

FIG. 2 is an equivalent circuit of a pixel forming part of the flatpanel detector illustrated in FIG. 1;

FIG. 3 is a schematic of a TFT switch array incorporating an ESD damageprotection circuit;

FIG. 4 is a cross-sectional view of FIG. 3;

FIG. 5 is another cross-sectional view of FIG. 3;

FIG. 6 is a schematic of an alternative embodiment of a TFT switch arrayincorporating an ESD damage protection circuit;

FIG. 7 is a top plan view of a portion of the TFT switch arrayillustrated in FIG. 6;

FIG. 8 is a top plan view of another portion of the TFT switch arrayillustrated in FIG. 6; and

FIG. 9 is a cross-sectional view of FIG. 7 taken along line 9--9.

BEST MODES FOR CARRYING OUT THE INVENTION

Referring now to FIG. 1, a flat panel detector for radiation imaging isshown and is generally indicated by reference numeral 20. The flat paneldetector includes a semiconductor switch array 21 in the form of aplurality of pixels 22 arranged in rows and columns. Gate lines 24interconnect the pixels 22 of each row while source lines 26interconnect the pixels of each column. The gate lines 24 lead to a gatedriver circuit 28 which provides pulses to the gate lines in successionin response to input from a control circuit 29. The source lines 26 leadto charge amplifiers 30 which in turn are connected to an analogmultiplexer 32. The analog multiplexer provides image output which canbe digitized to create a digitized radiation image in response to inputfrom the control circuit 29.

FIG. 2 shows an equivalent circuit of one of the pixels 22. As can beseen, the pixel 22 includes a radiation transducer CS. coupled to astorage capacitor C_(ST) in the form of a pixel electrode 36. The pixelelectrode 36 constitutes the drain electrode of a thin film transistor("TFT") switch 38. The source electrode of TFT switch 38 is coupled toone of the source lines 26 while the gate electrode of the TFT switch iscoupled to one of the gate lines 24.

When the radiation transducer C_(SE) is biased and is exposed toradiation, it causes the pixel electrode to store a charge proportionalto the exposure of the radiation transducer C_(SE), to radiation. Oncecharged, the charge can be read by supplying a gating pulse to the gateterminal of TFT switch 38. When the TFT switch receives the gate pulse,it connects the pixel electrode 36 to the source line 26 allowing thepixel electrode to discharge. The charge on the source line 26 isdetected by the charge amplifier 30 which in turn generates an outputvoltage proportional to the detected charge. The output voltage of thecharge amplifier is conveyed to the analog multiplexer 32.

Referring now to FIG. 3, during the fabrication process, the array 21 ofpixels 22 including the gate and source lines 24 and 26 respectively arefabricated on a common glass substrate. Wire bonding pads 46 are formedat the ends of the source lines 26 for testing or for wire bondingpurposes. Similarly, wire bonding pads 48 are formed at the ends of thegate lines 24. As mentioned previously, during fabrication of the TFTswitch array 21, during its testing or when connecting peripheralcircuits to the TFT switch array 21 such as gate driver 28 and chargeamplifiers 30, ESD damage to the TFT switch array may occur. To reducethe occurence of ESD damage during fabrication of the TFT switch array21, an ESD damage protection circuit 50 is also fabricated on the glasssubstrate as will now be described.

The ESD damage protection circuit 50 includes a first shorting elementin the form of a ring 52 surrounding the TFT switch array andinterconnecting all of the gate lines 24 of the TFT switch array 21.Specifically, the shorting ring 52 is connected directly to the wirebonding pads 48 on one side of the TFT switch array 21.

A second shorting element in the form of a ring 56 also surrounds theTFT switch array and interconnects all of the source lines 26 of the TFTswitch array 21. The second shorting ring 56 is connected directly tothe wire bonding pads 46 on one side of the TFT switch array 21 and isconnected to the wire bonding pads 46 on the other side of the TFTswitch array through resistive protection elements 58. Shorting ring 56is also connected to each of the wire bonding pads 48 on the other sideof the TFT switch array 21 through a resistive protection element 54.The two shorting rings 52 and 56 are electrically connected through vias(not shown) formed in the TFT switch array structure. The resistiveprotection elements 54, 58 provide current paths for leakingelectrostatic charges collected by the gate and source lines 24 and 26and have resistances at least one order of magnitude greater than theimpedance of the gate and source lines.

FIGS. 4 and 5 best illustrate the resistive protection elements 54 and58 respectively. As can be seen in FIG. 4, resistive protection element54 includes a Cadmium Selenide (CdSe) semiconductor material channel 78.Wire bonding pad 48 contacts the channel 78 through a via formed in thegate insulating layer 74 and passivation layer 76. Shorting ring 56 alsocontacts the channel 78. Resistive protection element 58 also includes aCdSe channel 78 contacted by wire bonding pad 46 and shorting ring 56.Shorting ring 56 as mentioned previously is connected to shorting ring52 through vias (not shown). The resistances of the resistive protectionelements 54 and 58 can be designed to change with bias voltage in alinear or non-linear manner and may take the form of one of a variety ofstructures such as for example, TFT switches, TFD's (thin film diodes),zener diodes or photodiodes.

As one of skill in the art will appreciate, the shorting ring 52 isformed when the gate lines 24 are being formed on the substrate of theTFT switch array structure. The shorting ring 56 is formed when thesource lines 26 are being formed on the substrate.

After the TFT switch array 21 and ESD damage protection circuit 50 havebeen formed on the glass substrate, the TFT switch array structure canbe cut along scribe lines ABCDA to expose the wire bonding pads 46 and48 connected to the source and gate lines extending from one side of theTFT switch array permitting the individual TFT switches 38 in the arrayto be tested. These scribe lines are marked so that part of eachshorting ring 52, 56 remains intact keeping the gate and source lines 24and 26 interconnected through the resistive protection elements 54 and58 during the testing stage. If electrostatic charges appear on the gateor source lines resulting in any unbalanced potentials across thedielectric film constituting the gate insulating layer of the TFT switcharray, the electrostatic charges will disperse quickly through theresistive protection elements connected to the gate and source lines.

Once testing has been completed, the outputs from the gate driver 28 canbe connected to the wire bonding pads 48 of the exposed gate lines 24via a wire bonding process. Similarly, the inputs to the chargeamplifiers 30 can be connected to the wire bonding pads 46 of theexposed source lines 26 via a wire bonding process. Thus, the TFT switcharray 21 can be connected to the peripheral circuitry with half of theESD damage protection circuit intact.

After the wire bonding processes have been completed, the remaining halfof the ESD damage protection circuit 50 can be severed from the TFTswitch array 21 using a laser cutting operation made along scribe linesEFG. However, the remaining half of the ESD damage protection circuitmay be useful when the flat panel detector 20 is in operation byallowing gate pulses applied to the gate lines to be fed back to thegate driver 28 to shape the gate pulse waveform or to reduce electronicnoise. In addition, the remaining connections between the resistiveprotection elements 54 and 58 and the shorting rings 52 and 56 permitsexcess charge to leak to ground, in the event that bond-wires peel offor in the event that defects in the charge amplifiers 30 or gate drivers28 occur.

In some applications especially in high resolution TFT liquid crystaldisplays and TFT flat panel detectors, it is desired to use peripheralcircuitry connected to the gate and source lines on both sides of theTFT switch array 21. Referring now to FIGS. 6 to 9, another embodimentof a TFT switch array 121 incorporating an ESD damage protection circuit150 is shown which is better suited to accommodate double-sidedperipheral circuitry. In this embodiment, like reference numerals willbe used to indicate like components with a ("100") added for clarity.

As can be seen, the ESD damage protection circuit 150 includes ashorting ring 152 interconnecting all of the gate lines 124 of the TFTswitch array 121. The shorting ring 152 is connected to only one end ofeach gate line 124 through wire bonding pads 148. The connectionsbetween the shorting ring 152 and the wire bonding pads 148 alternatebetween opposite sides of the TFT switch array. Shorting ring 152 alsointerconnects all of the source lines 126 of the TFT switch arraythrough vias formed in the TFT switch array structure. The shorting ring152 is connected to only one end of each source line 126 through wirebonding pads 146. The connections between the shorting ring 152 and thewire bonding pads 146 also alternate between opposite sides of the TFTswitch array 121.

A second shorting ring 156 is connected to the other end of each gateline 124 via resistive protection elements 154. Shorting ring 156 isalso connected to the other end of each source line 126 via resistiveprotection elements 158. The shorting rings 152 and 156 are electricallyconnected through vias 160 and 162 formed at the corners of the TFTswitch array structure (see FIGS. 7 and 8).

FIG. 7 best illustrates one of the resistive protection elements 154although it should be realized that both sets of resistive protectionelements 154 and 158 are similar. As can be seen, resistive protectionelement 154 includes a metal connection tab 170 contacting gate line 124through vias 172 formed in the gate insulating and passivation layers174 and 176 of the TFT switch array structure. The tab 170 contacts aCdSe semiconductor material channel 178. The shorting ring 156 alsocontacts the channel 178 but is spaced from the connection tab 170.

After the TFT switch array 121 and ESD protection circuit 150 have beenformed on the glass substrate, the TFT switch array can be cut alongscribe lines ABCDA to permit the individual TFT switches in the TFTswitch array to be tested. Similar to the previous embodiment, thescribe lines are marked so that after cutting, one end of each of thegate and source lines 124 and 126 remains connected to shorting ring 156via resistive protection elements 154 and 158 respectively.

Once testing has been completed, the peripheral circuits can beconnected to the exposed wire bonding pads 146 and 148 on opposite sidesof the TFT switch array 121. After this, the connections between thegate and source lines and the shorting ring 156 can be severed using aprogrammable laser cutting machine programmed to jump over the gate andsource lines 124 and 126 connected to peripheral circuits.

As one of skill in the art will appreciate, the ESD damage protectioncircuits are present from the first manufacturing stage of the TFTswitch array (gate line formation) right through to testing andconnection of the TFT switch array to peripheral circuits. Because ofthis, the likelihood of ESD damage occurring to the TFT switch array isreduced as compared to prior art switch arrays.

Although the ESD damage protection circuits have been described inconjunction with a TFT switch array used in a flat panel detector forradiation imaging, it should be apparent to those of skill in the artthat the ESD damage protection circuits can be fabricated during theformation of TFT switch arrays for other applications. Also, the ESDdamage protection circuits can be fabricated during the formation ofother semiconductor switch arrays where it is desired to protect theswitch array from ESD damage during its formation and testing.

Those of skill in the art will also appreciate that variations andmodifications may be made to the present invention without departingfrom the scope thereof as defined by the appended claims.

What is claimed is:
 1. A method of inhibiting electrostatic dischargedamage to an array of semiconductor switches formed on a commonsubstrate and arranged in rows and columns, individual ones of one ofthe rows or columns of said array being interconnected by source linesand individual ones of the other of the rows or columns of said arraybeing interconnected by gate lines, said method comprising the stepsof:during formation of said gate lines, connecting one end of each gateline directly to a shorting element and another end of each gate line toa shorting element via a protection element; during formation of saidsource lines, connecting one end of each source line directly to ashorting element and connecting another end of each source line to ashorting element via a protection element; and electrically couplingsaid shorting elements.
 2. The method of claim 1 further comprising thesteps of connecting said one and another ends of each of said sourcelines to a first shorting element, connecting said one end of each ofsaid gate lines to a second shorting element and said another end ofeach of said gate lines to said first shorting element and electricallycoupling said first and second shorting elements.
 3. The method of claim2 wherein said protection elements are in the form of resistiveprotection elements.
 4. The method of claim 3 wherein the one ends ofeach source line extend from one side of said array and said anotherends of each source line extend from an opposite side of said array andwherein the one ends of each gate line extend from one side of saidarray and said another ends of each gate line extend from an oppositeside of said array.
 5. The method of claim 3 further comprising the stepof initially cutting said array along a first set of scribe lines toexpose the one ends of said gate and source lines while maintaining theelectrical connection between the first and second shorting elements andthe another ends of said gate and source lines.
 6. The method of claim 5further comprising the step of further cutting said array along a secondset of scribe lines to sever the connection between said another ends ofsaid gate and source lines and said protection elements.
 7. The methodof claim 6 wherein said further cutting is performed using a lasercutting operation.
 8. The method of claim 1 further comprising the stepof connecting said one ends of said source and gate lines to a firstshorting element, connecting said another ends of said source and gatelines to a second shorting element and electrically coupling said firstand second shorting elements.
 9. The method of claim 8 wherein said oneand another ends of said source and gate lines alternate betweenopposite sides of said array.
 10. The method of claim 9 wherein saidprotection elements are in the form of resistive protection elements.11. The method of claim 10 further comprising the step of initiallycutting said array along a first set of scribe lines to expose the oneends of said gate and source lines while maintaining the electricalconnection between the first and second shorting elements and theanother ends of said gate and source lines.
 12. The method of claim 11further comprising the step of further cutting said array along a secondset of scribe lines to sever the connection between said another ends ofsaid gate and source lines and said protection elements.
 13. The methodof claim 12 wherein said further cutting is performed using a lasercutting operation.
 14. A semiconductor switch array incorporatingelectrostatic discharge protection comprising:an array of semiconductorswitches formed on a common substrate and arranged in rows and columns,the individual ones of one of the rows or columns of said array beinginterconnected by source lines and the individual ones of the other ofsaid rows or columns being interconnected by gate lines; and a pair ofelectrically coupled shorting elements formed on said substrate, each ofsaid gate and source lines being connected to one of said shortingelements directly and to one of said shorting elements via a protectionelement.
 15. A semiconductor switch array as defined in claim 14 whereinsaid protection elements are in the form of resistive protectionelements.
 16. A semiconductor switch array as defined in claim 15wherein one end of each source line is connected directly to one of saidshorting elements and the other end of each source line is connected tosaid one shorting element via said protection element and wherein oneend of each gate line is connected directly to another of said shortingelements and the other end of each gate line is connected to said oneshorting element via said protection element.
 17. A semiconductor switcharray as defined in claim 16 further including scribe lines to guidecutting thereof to expose said one ends of said gate and source lineswhile maintaining the electrical connection of said other ends of saidgate and source lines to said one and another shorting elements.
 18. Asemiconductor switch array as defined in claim 15 wherein one end ofeach of said source and gate lines is connected directly to one of saidshorting elements and wherein the other end of each of said source andgate lines is connected to another of said shorting elements via aprotection element.
 19. A semiconductor switch array as defined in claim18 wherein said one and other ends of said gate and source linesalternate between opposite sides of said array.
 20. A semiconductorswitch array as defined in claim 19 further including scribe lines toguide cutting thereof to expose said one ends of said gate and sourcelines while maintaining the electrical connection of said other ends ofsaid gate and source lines to said another shorting element.